Large-area electronic devices, such as flat panel displays, sensor arrays, and space antennas, typically include large-area sensor or light-emitting electronic cells that are addressed and/or controlled by thin film transistors (TFTs) and other electrical and electronic devices (e.g., passives and photodiodes). Such large-area electronic devices are expensive to make by conventional photolithography techniques due to the relatively large size of the electronic cell arrays (e.g., 1000 cm2 or larger), and the relatively large spacing between adjacent TFTs. Conventional photolithography equipment for fabricating typical (i.e., approximately 300 cm2 or smaller) IC devices is typically constructed to receive and process a semiconductor wafer having a predetermined size, and such wafers are typically much smaller than the substrate of a large-area electronic device. Therefore, specialized equipment for photolithography on large-area substrates must be developed typically at great expense. Moreover, conventional photolithography equipment includes optical and other processing tools that are constructed to facilitate the formation of substantially smaller feature sizes than those required in many elements of large-area electronic devices, thereby making the production of large-area electronic devices using such photolithography equipment highly inefficient.
Polymer semiconductor based field effect transistors are of particular interest for large-area electric device applications such as printed electronics on flexible substrates. However, the typical semiconductors used to make conventional polymer semiconductor based field effect transistors have low mobility (typically 0.001 cm2/Vs to 1 cm2/Vs). Therefore, the poor transconductance of these devices is a bottleneck for any application. One possible means to improve the transconductance is to improve the aspect ratio (channel width to channel length) of the transistor. However, improving the aspect ratio comes at the cost of layout area and feature size. Therefore, there appears a need for fine feature patterning of electrodes. While lithography can achieve fine features, it eliminates the possibility of low cost, roll to roll electronics which is the advantage of polymer electronics.
Jet-printing, offset printing and other printing techniques represent emerging technologies that attempt to reduce the costs associated with IC production for large-area electronic devices by replacing expensive photolithographic processing with simple printing operations, for example, in which layer structures are formed using nanoparticles and other materials in a solution that is ejected from a print head. By printing an IC pattern directly on a device substrate rather than using the delicate and time-consuming lithography processes used in conventional IC manufacturing, a jet-printing system can significantly reduce IC production costs. The printed IC pattern can either comprise actual IC features (i.e., elements that will be incorporated into the final IC, such as the gates and source and drain regions of TFTs, signal lines, the semiconductor, opto-electronic components, etc.), or it can be a mask printed onto the substrate that is used for subsequent semiconductor processing steps (e.g., etch, implant, etc.).
A problem with conventional jet-printing and other printing techniques is that the feature size (e.g., the width of each printed line) of printed structures is larger than desired in some large-area electronic devices, such as polymer semiconductor based field effect transistors. That is, the feature size of the pattern is limited by the printing technique, and is often much larger than is desired, particularly in the formation of TFTs. A reduction in feature size may be achieved by improving the printing system to pattern finer (smaller) features (e.g., using a smaller nozzle size for a jet-printer). However, most techniques are limited to a feature size of 30 microns or larger, which is often much larger than is desired, particularly in for the TFTs of a large-area electronic device.
Recent studies of the so-called coffee-stain effect have yielded speculation that the concentric lines formed by evaporating drops on horizontal surfaces may prove useful in the production of electronic devices. The phrase “coffee-stain effect” refers to the phenomenon in which solids dispersed in a drying drop will migrate to the edge of the drop and form solid rings. In theory, if the solid dispersed in the solution is conductive (e.g., silver nanoparticles), then the resulting solid “coffee-stain” rings may be used to produce electronic structures. However, due to the inconsistency of the curved or round shape of coffee-stain rings formed by conventional methods, conductive coffee-stain rings would have very limited practical application in the fabrication of electronic devices.
What is needed is a method for producing thin metal lines and other very fine features that may be utilized in the production of large-area electronic devices (e.g., polymer semiconductor based field effect transistors), avoids the problems (e.g., high-cost, low-resolution) associated with conventional techniques such as lithography and conventional printing techniques, and avoids the randomly-shaped “coffee-stain ring” structures produced using conventional receding puddle approaches.